晶體元件的(de)負(fu)(fu)載(zai)電(dian)(dian)(dian)容(rong)(rong)是指(zhi)在電(dian)(dian)(dian)路中(zhong)跨接(jie)晶體兩(liang)端(duan)的(de)總的(de)外界有效電(dian)(dian)(dian)容(rong)(rong)。是指(zhi)晶振(zhen)要(yao)正常震蕩(dang)所(suo)需(xu)要(yao)的(de)電(dian)(dian)(dian)容(rong)(rong)。一般外接(jie)電(dian)(dian)(dian)容(rong)(rong),是為了使晶振(zhen)兩(liang)端(duan)的(de)等(deng)(deng)效電(dian)(dian)(dian)容(rong)(rong)等(deng)(deng)于或接(jie)近(jin)負(fu)(fu)載(zai)電(dian)(dian)(dian)容(rong)(rong)。要(yao)求高的(de)場合還(huan)要(yao)考慮(lv)ic輸入端(duan)的(de)對(dui)地電(dian)(dian)(dian)容(rong)(rong)。應用時一般在給出負(fu)(fu)載(zai)電(dian)(dian)(dian)容(rong)(rong)值附(fu)近(jin)調(diao)整(zheng)可以得(de)到精(jing)確頻率。此(ci)電(dian)(dian)(dian)容(rong)(rong)的(de)大小主要(yao)影響負(fu)(fu)載(zai)諧(xie)(xie)振(zhen)頻率和等(deng)(deng)效負(fu)(fu)載(zai)諧(xie)(xie)振(zhen)電(dian)(dian)(dian)阻。
晶振的(de)負(fu)載電(dian)(dian)容=[(Cd*Cg)/(Cd+Cg)]+Cic+△C式(shi)中(zhong)Cd,Cg為分別接(jie)在晶振的(de)兩(liang)個腳上和對(dui)地的(de)電(dian)(dian)容,Cic(集成(cheng)電(dian)(dian)路內(nei)部電(dian)(dian)容)+△C(PCB上電(dian)(dian)容).就是(shi)說(shuo)負(fu)載電(dian)(dian)容15pf的(de)話(hua),兩(liang)邊(bian)個接(jie)27pf的(de)差不多了(le),一(yi)般a為6.5~13.5pF
各種邏輯芯(xin)(xin)(xin)片(pian)的(de)(de)(de)(de)(de)(de)(de)晶(jing)(jing)振(zhen)(zhen)(zhen)引(yin)(yin)(yin)腳可以(yi)等(deng)效(xiao)為電(dian)(dian)(dian)容(rong)三(san)點(dian)(dian)(dian)式(shi)(shi)振(zhen)(zhen)(zhen)蕩器(qi)(qi)(qi)。晶(jing)(jing)振(zhen)(zhen)(zhen)引(yin)(yin)(yin)腳的(de)(de)(de)(de)(de)(de)(de)內(nei)部通(tong)(tong)常(chang)是(shi)(shi)(shi)(shi)(shi)一(yi)(yi)(yi)個反(fan)(fan)相器(qi)(qi)(qi), 或(huo)(huo)者(zhe)是(shi)(shi)(shi)(shi)(shi)奇數(shu)(shu)個反(fan)(fan)相器(qi)(qi)(qi)串(chuan)聯(lian)(lian)。在(zai)晶(jing)(jing)振(zhen)(zhen)(zhen)輸(shu)出(chu)引(yin)(yin)(yin)腳 XO 和晶(jing)(jing)振(zhen)(zhen)(zhen)輸(shu)入(ru)(ru)引(yin)(yin)(yin)腳 XI 之(zhi)間(jian)用一(yi)(yi)(yi)個電(dian)(dian)(dian)阻連接(jie)(jie), 對(dui)于 CMOS 芯(xin)(xin)(xin)片(pian)通(tong)(tong)常(chang)是(shi)(shi)(shi)(shi)(shi)數(shu)(shu) M 到數(shu)(shu)十 M 歐之(zhi)間(jian)。很(hen)多芯(xin)(xin)(xin)片(pian)的(de)(de)(de)(de)(de)(de)(de)引(yin)(yin)(yin)腳內(nei)部已經包(bao)含了這個電(dian)(dian)(dian)阻, 引(yin)(yin)(yin)腳外部就(jiu)不(bu)用接(jie)(jie)了。這個電(dian)(dian)(dian)阻是(shi)(shi)(shi)(shi)(shi)為了使反(fan)(fan)相器(qi)(qi)(qi)在(zai)振(zhen)(zhen)(zhen)蕩初始(shi)時處與線性狀態, 反(fan)(fan)相器(qi)(qi)(qi)就(jiu)如同(tong)一(yi)(yi)(yi)個有很(hen)大增(zeng)益(yi)的(de)(de)(de)(de)(de)(de)(de)放大器(qi)(qi)(qi), 以(yi)便于起(qi)振(zhen)(zhen)(zhen)。石(shi)英晶(jing)(jing)體(ti)(ti)(ti)也連接(jie)(jie)在(zai)晶(jing)(jing)振(zhen)(zhen)(zhen)引(yin)(yin)(yin)腳的(de)(de)(de)(de)(de)(de)(de)輸(shu)入(ru)(ru)和輸(shu)出(chu)之(zhi)間(jian), 等(deng)效(xiao)為一(yi)(yi)(yi)個并聯(lian)(lian)諧(xie)(xie)振(zhen)(zhen)(zhen)回(hui)路(lu)(lu), 振(zhen)(zhen)(zhen)蕩頻率(lv)應該是(shi)(shi)(shi)(shi)(shi)石(shi)英晶(jing)(jing)體(ti)(ti)(ti)的(de)(de)(de)(de)(de)(de)(de)并聯(lian)(lian)諧(xie)(xie)振(zhen)(zhen)(zhen)頻率(lv)。晶(jing)(jing)體(ti)(ti)(ti)旁邊(bian)的(de)(de)(de)(de)(de)(de)(de)兩(liang)(liang)個電(dian)(dian)(dian)容(rong)接(jie)(jie)地(di), 實際上就(jiu)是(shi)(shi)(shi)(shi)(shi)電(dian)(dian)(dian)容(rong)三(san)點(dian)(dian)(dian)式(shi)(shi)電(dian)(dian)(dian)路(lu)(lu)的(de)(de)(de)(de)(de)(de)(de)分(fen)壓電(dian)(dian)(dian)容(rong), 接(jie)(jie)地(di)點(dian)(dian)(dian)就(jiu)是(shi)(shi)(shi)(shi)(shi)分(fen)壓點(dian)(dian)(dian)。以(yi)接(jie)(jie)地(di)點(dian)(dian)(dian)即分(fen)壓點(dian)(dian)(dian)為參考點(dian)(dian)(dian), 振(zhen)(zhen)(zhen)蕩引(yin)(yin)(yin)腳的(de)(de)(de)(de)(de)(de)(de)輸(shu)入(ru)(ru)和輸(shu)出(chu)是(shi)(shi)(shi)(shi)(shi)反(fan)(fan)相的(de)(de)(de)(de)(de)(de)(de), 但從并聯(lian)(lian)諧(xie)(xie)振(zhen)(zhen)(zhen)回(hui)路(lu)(lu)即石(shi)英晶(jing)(jing)體(ti)(ti)(ti)兩(liang)(liang)端(duan)(duan)來看, 形成一(yi)(yi)(yi)個正反(fan)(fan)饋(kui)以(yi)保證電(dian)(dian)(dian)路(lu)(lu)持(chi)續振(zhen)(zhen)(zhen)蕩。在(zai)芯(xin)(xin)(xin)片(pian)設計時, 這兩(liang)(liang)個電(dian)(dian)(dian)容(rong)就(jiu)已經形成了, 一(yi)(yi)(yi)般是(shi)(shi)(shi)(shi)(shi)兩(liang)(liang)個的(de)(de)(de)(de)(de)(de)(de)容(rong)量(liang)相等(deng), 容(rong)量(liang)大小依(yi)工藝(yi)和版圖(tu)而(er)不(bu)同(tong), 但終歸(gui)是(shi)(shi)(shi)(shi)(shi)比較小, 不(bu)一(yi)(yi)(yi)定適合(he)很(hen)寬的(de)(de)(de)(de)(de)(de)(de)頻率(lv)范圍。外接(jie)(jie)時大約是(shi)(shi)(shi)(shi)(shi)數(shu)(shu) PF 到數(shu)(shu)十 PF, 依(yi)頻率(lv)和石(shi)英晶(jing)(jing)體(ti)(ti)(ti)的(de)(de)(de)(de)(de)(de)(de)特性而(er)定。需(xu)要注意的(de)(de)(de)(de)(de)(de)(de)是(shi)(shi)(shi)(shi)(shi):這兩(liang)(liang)個電(dian)(dian)(dian)容(rong)串(chuan)聯(lian)(lian)的(de)(de)(de)(de)(de)(de)(de)值是(shi)(shi)(shi)(shi)(shi)并聯(lian)(lian)在(zai)諧(xie)(xie)振(zhen)(zhen)(zhen)回(hui)路(lu)(lu)上的(de)(de)(de)(de)(de)(de)(de), 會影響振(zhen)(zhen)(zhen)蕩頻率(lv)。當兩(liang)(liang)個電(dian)(dian)(dian)容(rong)量(liang)相等(deng)時, 反(fan)(fan)饋(kui)系(xi)數(shu)(shu)是(shi)(shi)(shi)(shi)(shi) 0.5, 一(yi)(yi)(yi)般是(shi)(shi)(shi)(shi)(shi)可以(yi)滿足振(zhen)(zhen)(zhen)蕩條件(jian)的(de)(de)(de)(de)(de)(de)(de), 但如果(guo)不(bu)易起(qi)振(zhen)(zhen)(zhen)或(huo)(huo)振(zhen)(zhen)(zhen)蕩不(bu)穩(wen)定可以(yi)減小輸(shu)入(ru)(ru)端(duan)(duan)對(dui)地(di)電(dian)(dian)(dian)容(rong)量(liang), 而(er)增(zeng)加輸(shu)出(chu)端(duan)(duan)的(de)(de)(de)(de)(de)(de)(de)值以(yi)提高反(fan)(fan)饋(kui)量(liang)。
設計考慮(lv)事項(xiang):
1、使(shi)晶振、外部電(dian)容器(如果有)與(yu) IC之(zhi)間的(de)信號線(xian)盡可能保(bao)持短(duan)。當非(fei)常(chang)低的(de)電(dian)流通過IC晶振振蕩器時,如果線(xian)路(lu)太長(chang),會使(shi)它對 EMC、ESD 與(yu)串擾產生(sheng)非(fei)常(chang)敏感(gan)的(de)影響(xiang)。而且長(chang)線(xian)路(lu)還(huan)會給振蕩器增加寄生(sheng)電(dian)容。
2、盡可能將其它時(shi)鐘線路與頻繁切換的(de)信(xin)號線路布置在遠離(li)晶振連接的(de)位(wei)置。
3、當心晶振(zhen)和地的(de)走線
4、將晶振外(wai)殼接地
如果實際的(de)負(fu)載電(dian)容配置不當,第一會引起(qi)線路(lu)參考頻(pin)率(lv)的(de)誤差。另(ling)外如在發射接收電(dian)路(lu)上(shang)會使晶振(zhen)的(de)振(zhen)蕩幅(fu)度下降(不在峰(feng)點),影響混頻(pin)信號(hao)的(de)信號(hao)強度與信噪。
當(dang)波(bo)形(xing)(xing)出現削峰,畸變時,可增加負載電(dian)阻(zu)調整(幾十K到幾百(bai)K).要穩定波(bo)形(xing)(xing)是(shi)并聯一個1M左右的(de)反饋(kui)電(dian)阻(zu)。